In recent years, there has been a trend in rapid development of smaller SRAMs and scaling down of the power source voltage. As a result, data errors (Soft Error Rate, referred to as SER hereinafter) in semiconductor memory devices such as SRAMs tend to increase. For example, the widely used 6-transistor SRAM has no particular provisions for ensuring a capacitance of 50 fF or more as with the capacitors of conventional DRAMs. Specifically, for SRAM designed to perform logical processes, SERs are more pronounced than in general-purpose DRAMs. If such scaling continues, it is believed that the SER problem will become more important, and will be a major problem in the scaling of SRAMs.
This danger grows due to the increase in the on-chip memory capacitance in DSPs. For example, when it is used as data memory, the error operation due to a data error of 1 bit is not a major problem. However, when it is used as program memory, even a data error of 1 bit may lead to control failures of DSPs.
In the prior art, to counteract SERs in general-purpose DRAMs, the technology for error checking and correction (hereinafter referred to as FCC) is adopted. However, in general-purpose DRAMs, the operation performed on the system level is preferred over that by means of on-chip ECC with respect to cost, reliability and performance. Now, with progress in the semiconductor manufacturing technology, the semiconductor devices become smaller and the power source voltage becomes lower. For cDSP that carries DSP, ARM, etc. that form the system on-chip, the necessity for solving this problem at the chip level becomes more and more important.
Examples of typical ECC algorithms include Hamming code system, vertical-horizontal parity system, etc. In the conventional DRAM, the following system is usually adopted: in the latter stage of the input circuit used for writing, the ECC circuit is set to generate ECC code, which, together with the data code, is stored in a prescribed memory region. During a read operation, the ECC code is read together with the data code, and by means of an ECC circuit set on the output side of a sense amplifier, the error of the data code is detected and corrected on the basis of the data code and ECC code.
However, the aforementioned conventional error correction system that uses the ECC circuit has some disadvantages. Since an ECC circuit is connected in series downstage to the read circuit, the data read speed is reduced. In addition, use of the ECC circuit leads to an increase in the circuit size and increase in the power consumption.
Several methods for decreasing the SER without using an ECC circuit have been proposed, such as a method in which the storage capacity of the memory node of the SRAM is increased so as to prevent damage to the stored data, a method in which voltage of the storage node of the SRAM is raised, etc. However, these methods also have disadvantages. When the capacity of the storage node is increased, it is necessary to introduce a DRAM or a special process, and the cost increases. Also, the circuit size inevitably becomes larger. When the voltage at the storage node is raised, reduction in feature size of the SRAM is limited, SRAM performance diminishes, and power consumption and costs increase.
In addition, there is another method in which the SRAM is formed on an insulated substrate instead of a silicon substrate, that is, the so-called SOI (Semiconductor On Insulator). However, this method is not very effective in improving the SER. Also, a method for improving the data reliability by introducing ferroelectric memory (FeRAM) has been proposed. However, mass production technology has not been developed for this method.
The objective of the present invention is to solve the aforementioned problems of the conventional methods by providing a type of semiconductor memory device that has an error correction circuit which can correct errors in the stored data without increasing the circuit size and power consumption or decreasing the operating speed.